The processor MIAOW is a resistor-transistor logic implementation of AMD’s open source Southern Islands instruction set architecture. A white paper has been published on the device by the researchers. It took 36 months for a core team of 12 visionary developers to develop MIAOW. Their goal was simply to create a functional GPGPU without setting any specific area, frequency, power or performance goals.
It may be sensible to think that as an open source project, once it is further developed, some clever business might decide to take the chip into full production. This may also result in some serious IP violation issues that might have to be addressed. As the complete scope of the project is dependent on a trimmed down version of the AMD ISA for its own GPUs, the team will either need to work within AMD’s limitations to constantly push such a project or the effort, irrespective of how well established it is in FPGA prototyping or actual silicon, could be a number of lawsuits waiting in the pipeline to occur.
Computer Scientist Karu Sankaralingham, who leads the Wisconsin research group explains that the creation of MIAOW is the recent in a series of actions taken to keep processor development in line with Moore’s Law. “We need innovative new hardware modules, new types of processors, new types of hardware accelerators, and so on,” he says. Open source hardware represents a promising new avenue. “I envision five, ten years from now companies will be leveraging open-source hardware, just like it happened with open-source software,” says Sankaralingham. “For example, Facebook was built mainly using PHP. PHP is completely open source. It would be hard to imagine that Facebook would have gotten off the ground if PHP wasn’t there.” When AMD made the Instruction Set Architecture of one of its graphics processors available, Sankaralingham and his team decided to concentrate on a graphics processor. The CPUs have been increasingly being replaced by Graphics processors for tackling high-performance computing and crunching big data. “What GPGPUs are good at is using GPU architecture to tackle highly computationally intense problems,” says Sankaralingham. “Their architectures have two important properties: They provide very high performance and they are very power efficient.” As a result, GPUs will be used in, for instance, navigation systems, the Internet of Things, driverless cars, and deep learning. The Wisconsin researcher pointed out that there is a huge need for very high computation speed at low power use in all of these environments. Currently, MIAOW is strictly an academic research project, as it does not posses the auxiliary logic required to create actual graphical output and lacks the logic needed to connect it to a specific memory or system bus. “One impact it will have in my field,” says Sankaralingham, “is that academic researchers, who have a very low-level hardware implementation in their research, are going to adopt our ideas.” The group’s work another significant result is that it has “demonstrated that smart teams can go and build meaningful hardware parts that can compete with high-end industrial products.” Sankaralingham says he views his group’s research as a stepping stone to the developing of totally clean-slate designs that do not depend on any commercial products that are existing in the industry. The MIAOW GPU is basically a stripped-down version of commercial GPUs. It implements a subset of the AMD GPU instruction set. The current GPU design includes a host CPU that assign a kernel to the GPGPU, a memory controller, and a cached memory hierarchy. The resulting GPGPU in its current design uses just 95 instructions and 32 compute units. It only supports single-precision operations. But research team are reportedly in the process of adding a graphics pipeline to the current GPU design, a process expected to take about six months. With the advancement in technology, MIAOW may prove to be a milestone in the computer hardware industry.
